Conventional interfaces typically use either a return-to-zero signaling scheme or a non-return-to-zero signaling scheme. Return-to-zero (RZ) signaling refers to a signaling scheme in which the signal returns to zero between each pulse. The signal returns-to-zero between pulses even if a number of consecutive zeros or ones occur in the signal. Since the signal returns to zero between each pulse, a separate clock signal is, typically, not needed in the RZ signaling scheme.
Non-return-to-zero (NRZ) refers to a signaling scheme in which logic highs are represented by one significant condition and logic lows are represented by another significant condition with no neutral or rest condition. Since the pulses do not have a rest state, a synchronization signal is typically sent alongside the data signal.
Three dimensional (3D) die stacking refers to vertically integrating two or more die with, for example, a dense, high-speed interface. One or more of the stacked die may include a bus for which I/O needs to be performed. The bus may include a number of bit lines and each bit line may have a different length. In conventional systems, bit lines are length matched using, for example, delay buffers. The use of delay buffers to length match the bit lines can significantly increase the complexity of designing a die. Delay buffers may also lower performance by increasing latency (e.g., due to inverters in the signal path).